1. Field of the Invention
The present invention broadly relates to VLSIs and, more particularly, to a MIS transistor, as well as to a method of producing the same.
2. Description of the Related Art
In general, a very large scale integrated circuit (VLSI) incorporates many very small MIS transistors. As a consequence, hot-electron degradation of a device under application of a high level of electrical field and parasitic capacitance have become a matter of great concern. In addition, the formation of very-small transistors require a production process which employs self-aligning technique. A MOS transistor, as an example of the conventional MIS transistors, is disclosed in IEEE ELECTRON DEVICE LETTERS Vol. 11, No. 2, 1990, p78-81. FIG. 2 is a cross-sectional view of this MOS transistor.
Referring to FIG. 2 which is a sectional view, the MOS transistor has a P-type semiconductor substrate 21, a gate oxide film 22 formed on the P-type semiconductor substrate 21, an N-type polysilicon gate electrode 23 formed on the gate oxide film 22, a thin oxide film 24 which is formed on the device region so as to cover the N-type polysilicon gate electrode 23, a polysilicon gate side wall 25 formed on the thin oxide film 24, an N-type low-density diffusion layer 26 formed on the p-type semiconductor substrate 21, and an N-type high-density diffusion layer 27 formed on the P-type semiconductor substrate 21. Numeral 28 denotes a passivation film on the device, while 29 designates a wiring laid on the passivation film 28.
In the MOS transistor having the described construction, when a voltage is applied to the N-type polysilicon gate electrode 23, current flows between the source and the drain of the N-type high-density diffusion layer 27, so that an electric field of a high level around the drain is reduced by the polysilicon gate sidewall 25, which has a high dielectric constant, e.g., 3 times as large that of the silicon oxide film which is an ordinary gate side wall, whereby hot-electron degradation is suppressed. Conversely, when no voltage is applied to the N-type polysilicon gate electrode 23, no current flows between the source and the drain of the N-type high-density diffusion layer 27, so that the MOS transistor functions as a switch.
The above-described MIS transistor encounters with the following problems due to the use of the conductive polysilicon gate side wall 25. When the electrical contact is to be attained in a self-aligning manner, a short-circuit is caused between the polysilicon gate side wall 25 and the wiring 29 laid on the side wall 25. The production of this MIS transistor, therefore, requires series of steps including, after the formation of the polysilicon gate side wall 25, depositing the passivation film 28 on the sidewall 25, and forming a contact hole by masking for attaining an electrical contact between the N-type high-density diffusion layer 27 and the wiring 29.
Another problem resides in that the material of the conductive polysilicon gate side wall 25 undesirably remains, without being etched, if any height difference in the device region, e.g., a recess formed between adjacent devices, causes an error in the wiring. In order to avoid such a wiring error or short-circuit mentioned before, it is necessary to lay the passivation film 28 thereover as shown in FIG. 2, which is quite inconvenient from the view point of the production of very large scale integrated circuit incorporating very small transistors.
Furthermore, the use of the polysilicon gate side wall 25 having a high dielectric constant increases the parasitic capacitance C between the wiring 29 laid above the gate and the polysilicon gate electrode 23, which causes a retardation of the speed of switching of the MOS transistor.